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NCL30001
I p
I spos
+
?
g m = 250 m S
g m
blanking
t LEB
Inst. current
To PWM
comparator
R CS
Current sense
amplifier
C IAVG
I AVG
R IAVG
V IAVG
To AC error
amplifier
Figure 54. Current Sense Amplifier
I CS + I IN + (eq. 3)
C IAVG +
Caution should be exercised when designing a filter
between the current sense resistor and the IS POS input, due
to the low impedance of this amplifier. Any series resistance
due to a filter creates a voltage offset (V OS ) due to its input
bias current, CA Ibias . The input bias current is typically
60 m A. The voltage offset is given by Equation 2.
V OS + CA Ibias @ R external (eq. 2)
The offset adds a positive offset to the current sense signal.
The ac error amplifier will then try to compensate for the
average output current which appears never to go to zero and
cause additional zero crossing distortion.
A voltage proportional to the main switch current is
applied to the IS POS pin. The IS POS pin voltage is converted
into a current, i 1 , and internally mirrored. Two internal
currents are generated, I CS and I AVG . I CS is a high frequency
signal which is a replica of the instantaneous switch current.
I AVG is a low frequency signal. The relationship between
V ISPOS and I CS and I AVG is given by Equation 3.
V ISPOS
4k
The PWM Output delivers current to the positive input of
the PWM input where it is added to the AC EA and ramp
compensation signal.
The I AVG Output generates a voltage signal to a buffer
amplifier. This voltage signal is the product of I AVG and an
external R IAVG resistor filtered by the capacitor on the I AVG
pin, C IAVG . The pole frequency, f P , set by C IAVG should be
significantly below the switching frequency to remove the
high frequency content. But, high enough to not to cause
significant distortion to the input full wave rectified
sinewave waveform. A properly filtered average current
signal has twice the line frequency. Equation 4 shows the
relationship between C IAVG (in nF) and f P (in kHz).
1
(eq. 4)
2 @ p @ R IAVG @ f P
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